These include some of the most common components I use in simulations (which may be generic, or from forgotten sources; attribution is given where possible), and components that I have created models for, based on datasheet properties or actual measurements.
1N4148.mdl Common diode. Unknown source. Notable differences: RS is modest; some models have it unusually large. CJO is probably way too small though. Fitness not confirmed by measurement in SPICE or IRL.
BAV99S.ckt Common dual diode. Commented out: 1N4148 model as alternative, parasitics for convergence. Model from Diodes, Inc.
b340a.ckt Common power schottky diode. Source: Thomatronik GmbH. Added approximate package parasitics (adjust CP to trade off convergence for capacitance accuracy).
2N3904.mdl Common NPN. Unknown source. May slightly overestimate hFE. Note: MODELs do not include package parasitics or breakdown voltage.
2N3906.mdl Common PNP. Unknown source. May slightly overestimate hFE. Note: MODELs do not include package parasitics or breakdown voltage.
Logic models, mostly analog equivalents as no one can decide on a common digital backend (XSPICE stinks; Altium uses SimCode; Multisim uses their own custom code; LTspice uses proprietary behavioral models, etc.).
HC7014.ckt Behavioral model of the 74HC7014 hex precision schmitt trigger buffer.
BEH_LOGIC.ckt I created a full analog logic family. Supply consumption, input diodes, output current, propagation delay and slew rate are all modeled.
CD4001_TR.ckt Quite possibly the first public full model of a CMOS gate, including ESD diodes and parasitic transistors. Uses models from Dr. Lynn F. Fuller. Models adjusted to match real component measurements.
CD4011_M.ckt Hybrid of BEH_LOGIC and the Fuller models, for modeling output characteristics.
CD4043.ckt Approximate CD4043 model. TODO: resolve XSPICE suckiness. This should be a very simple thing to model but it isn't obvious how to solve it while avoiding metastability (XSPICE gates have unlimited bandwidth: there is no toggle rate limit) or error states (an SR latch cannot be driven both inputs high).
CD4069U_AN.ckt Full model, including parasitic BJTs. Uses Dr. Fuller's models.
C_CJO.ckt Models diode junction capacitance explicitly as a nonlinear capacitor. Created for use with MOSFETs. Note: a lot of models use a dependent Cdg, but this is wrong: VDMOS types do not depend on gate voltage, only VDS. C_CJO2 allows this to be modeled correctly as well.
MCP6561.ckt Fixed for 3f5 compatibility and convergence. Based on the model by Microchip, Inc. Original used very sharp TABLE sources. I converted these to diode-clamped current sources, which have similar behavior with softer thresholds, and most importantly, continuous derivatives. Supply current also modeled continuously (overkill). Hysteresis modeling (commented out) may be broken. Note: hysteresis invokes SN74F04 code model in Altium's built-in library.
zener.ckt Parameterized voltage zener diode model. Characteristics closest to a 1N5231 (at default Value); not meant to represent any particular part at other voltages.
rth.ckt Basic first-order Steinhart-Hart model. Enter parameters as given in the part datasheet (e.g., rated resistance at 25°C and B at 25/85°C). (The first-order equation is adequate to get within maybe 5 or 10% of actual value of real parts, over full temperature range.)
Coilcraft_Model.ckt General purpose inductor model, including core loss, skin effect and one high-frequency pole-zero pair. Works in most simulators in AC Analysis; does not work (or works very poorly) in Transient Analysis. Source: Coilcraft Inc. See my Coilcraft Model Converter for a universal version.
rdiff.ckt Warburg element (diffusion resistance) over 4-decade range. Used with the Coilcraft model converter. See discussion for more information.
ASH.ckt Analog sample-and-hold function. Performs a FIR filtering operation followed by a zero-order hold. Output updates at 2*Period. Typical use case: reducing ripple in an averaged value. Example: measuring DC current, power dissipation, etc. Output can stabilize faster than a comparable operation like INT(V(Vin,0)) / (time + 1u). Details
INDSAT.ckt Saturable inductor / core model. Many libraries provide a nonlinear core model framework, using flux as the common variable; this uses in-circuit values directly. Includes commented-out convergence tweaks. Typical use case: as-is for a single winding on a ferrite core; to model multi-winding transformers, use ideal transformers, series leakage inductors, DC resistances and stray capacitors.
INVPWR.ckt Shortcut power supply model, with various parasitics included. (TODO: draw a schematic to illustrate this.)
RLCPAR.ckt Shortcut RLC parallel equivalent network. Typical use case: inductor with parasitics.
RLCSER.ckt Shortcut RLC series equivalent network. Typical use case: capacitor with parasitics.