Back in 2008 or so, I was playing with various switching and control ideas. To solidify those concepts, I designed this amplifier. Overall specs: power level 10W, 8 ohm load, audio frequency response (20-20kHz, DC coupling allowable), efficiency over 70%. I created the design in Multisim 11 and tweaked the simulation until I had satisfactory results. I then created a two-layer circuit board layout in Ultiboard. Some circuits I evaluate on the solderless breadboard; due to the surface mount design and ground plane requirement, this circuit needed a PCB. (These days, I often go for "dead bug" style construction, which saves the layout of a PCB, and performs well, but tends to produce... less attractive results.) I manufactured the PCB by hand, using the toner transfer method and a cupric chloride etching bath of my own formulation. After assembly, testing verified that the simulation was reasonably correct, differing in high frequency transients (of course), but it managed to estimate overall efficiency within a few percentage points of measured results.
This is the block diagram. The basic design is a textbook voltage-mode pulse width modulator: it uses a ramp oscillator, comparing the ramp voltage to the input signal voltage to generate PWM. Three minor additions round out the design: on the input, an error amplifier to reduce distortion; a power amplifier section, of course; and, since the amplifier is "bridged" (an H-bridge), so that both outputs are live, a differential amplifier to sense the output voltage.
We can already draw some conclusions about the circuit. Linearity of the PWM generator itself depends on the ramp generator, which isn't very good — the diagram shows exponential decay style curves, not a pure triangle wave. The error amplifier serves to correct this, but it can only do so asymptotically over time. The error amplifier has to be slowed down enough so that it can make sense of the signal feeding back into it, which means the loop gain (which reduces distortion) will be excellent at low frequencies, but will roll off at higher frequencies, where the residual distortion will be more noticeable.
A classic astable multivibrator was used for the ramp generator:
An LM393 comparator is used as a basic building block. Sometimes I'll build a discrete circuit for the sake of building it that way, but it's not usually worth building differential amplifiers; that's a solved problem. Comparators and op-amps are general enough that they fit very well with a discrete design philosophy. Another reason for discrete is, simulation is more-or-less guaranteed to work (given the limitations of a simulated environment), whereas manufacturers rarely provide models for special-purpose chips, completely precluding any simulation of that function of the circuit. General-purpose devices, like comparators and op-amps, typically have good models available (though there are some exceptions, like the common TL431 macro model, which some have taken it upon themselves to address).
Here are the waveforms: the square wave at the emitter follower, and the ramp on the timing capacitor. The square wave has a somewhat sluggish rise, due to the 10k pullup resistor and node capacitances, while the falling edge is fairly prompt due to the comparator's open collector output and the emitter-base diode. The ramp alternates between 4.08 and 7.91V, very nearly 1/3 and 2/3 the supply voltage. The switch points aren't exactly thirds, because the emitter follower doesn't pull all the way up to the supply, nor all the way down to ground. The voltage drops (from supply and ground) depend on diode drops, so will be somewhat temperature sensitive; the overall error in amplitude, offset and frequency should be less than 5-10% over the commercial temperature range.
Actual measurement (2V/div vertical, both channels centered one div from the bottom, 2μs/div horizontal). The scope probes probably weren't compensated quite right (the square wave has a lazy sloping skew to it, which isn't a property of anything in this circuit), but the voltages and frequency are very close to the simulation.
Since this is a single-supply circuit, the error amplifier has to rest on a virtual ground, formed by a resistor and capacitor divider near the input. A common alternative is to buffer a voltage divider with an op-amp, to provide a regulated Vcc/2 node, but that would require another op-amp. Without one to spare, this simple solution is at the mercy of currents directed into it. Fortunately, only two branches feed in: the 10k resistor from the output's voltage divider, and the 10k divider to the error amp's inverting input. The output swings -6 to +6V, so the divider sees ±1.2V on the 10k resistor, or ±0.12mA. The sense amp has a gain of 1/5, so its output swings ±1.2V as well, which puts ±0.06mA into ground at the other resistor. Both currents together span ±0.18mA, which cause an error of ±0.9V on the ground node. This leaves plenty of room, and the op-amps are in no danger of running out of common mode range or clipping.
Errata: I don't know why I chose to divide the feedback signal by half. The sense signal is well within common mode range, and gain can be increased by raising the output sense resistors (say, 100k instead of 47k). The resistor to ground may be a relic from playing with compensation methods on the inverting node, such as R+C to ground, or pole-zero compensation (placing an R+C across the resistor from sense out to inverting in). Not sure!
This is a somewhat unusual bit of circuitry, not something that's typically seen. Not that discrete gate drives are all that common anyway. First off: operation. Because the output is H-bridge, complementary drive signals are required. A naïve method might use a digital logic inverter to produce the complement (at some delay); a CD4069 would do well enough. But this delays the complement unnecessarily. Surely there must be a simple, elegant solution. I wouldn't claim to have an elegant solution, but what I found seems to do well enough: taking some advantage of the comparator's open collector output, I've married a common-emitter inverter with a common-base buffer. The comparator's output must pull below one diode drop when on, and will rise to two diode drops when off.
When the comparator turns on, a speed-up capacitor helps yank charge out of the common-emitter inverter (reducing storage time), and turns on the common-base buffer. As the buffer turns on, its collector voltage falls, until it saturates; because hFE falls in saturation, the base voltage gets shunted down, which is acceptable because the double-diode voltage reference is current limited. Indeed, this is desirable, because limiting base current also limits stored charge. Note that the comparator must sink the buffer's collector current, one downside of this method. An additional inverting transistor could be inserted between this circuit and the comparator, to increase the pull-down current available, and therefore, the output sink current.
When the comparator turns off, the buffer's emitter current goes away, and its collector current sucks stored charge out of the base, turning it off fairly quickly. The 10k pull-up on the input causes its voltage to rise, until the diode and common-emitter transistor are forward biased. (The 470pF cap will be somewhat discharged as well, providing some speed-up action.)
To provide consistent drive over a wide voltage swing, 15mA current sources are used for pull-up action. A naïve solution might use two independent current sources, or just as well, one might naïvely tie them together (noting the redundant bias circuit), as done here. Whether naïve or not, the solution shown is preferred: when one current source saturates, the lack of collector current causes its emitter voltage to pull closer to Vcc, pulling the base voltage up as well. Normally, this reduces or turns off the other sources—at the very least, an inconvenient mistake in an audio amplifier, for example—but because these outputs are complementary, it's actually quite beneficial: when one side is saturated, the opposing side is being held at ground by the driven switch; sourcing current would burn full supply voltage, while weakening its pull-down capability. By (mostly) turning off the opposing source, this driver achieves reasonable efficiency: like CMOS, current is only drawn during switching events.
Finally, the output voltages are beefed up with complementary emitter followers. The current sources and open collectors are not sufficient to drive gates by themselves, and need some help. The logic produces a voltage swing within a few Vce(sat) of supply or ground, so the additional diode drop of an emitter follower is more-or-less tolerable. (One alternative would be to buffer it with a CMOS inverter made from discrete MOSFETs: the unbuffered outputs have enough capacity to drive small enough gates, which in turn have enough drive capacity to switch the output transistors. An open-drain output also swings fully rail-to-rail. 2N7002 and BSS84 are typically used as more-or-less complementary transistors and would be good candidates.)
The simulated gate drive waveforms (one pair of edges). The opposite edges have slightly more delay between them, due to remaining difference in storage and turn-on/off time of the buffer and inverter transistors. The difference can be tuned some by the 470pF "speed-up" cap on the inverter.
Actual waveforms as measured in circuit (2V/div vertical, both channels; channel 2 colorized to stand out; 50ns/div horizontal). Skew is a bit worse (about 30ns, versus about 10ns simulated), and rise time similar or a bit better. Transients are different, for many reasons: differences in circuit inductance and capacitance are dominant, but even silly things, like how SPICE simulates gate capacitances (and how manufacturers' models attempt to address it), have a significant impact on the waveforms seen. One feature worth drawing attention to: since the green trace turns on first, supply bounce causes the purple trace to dip immediately by about 1.5V for 10ns (coincident with the little zig-zag on the green trace). It then returns for about 20ns, then swings in earnest. Both waveforms have trash following the event, due to supply bounce (including ground bounce, and probably some probe grounding error too). Residual charge (Miller effect, etc.) causes the purple trace to hover above ground about a volt, corresponding to the saturation voltage of the gate drive emitter followers.
The FDS8333C was an aging product (in fact, obsoleted in 2011!), but back in the day, I had picked up a baggie of them for relatively cheap (probably why!), and I've been using them here or there since. Short specs: complementary pair, SO-8 package, 30V, 4A, max 220mΩ Rds(on), max 6.6nC Qg. Many drop-in equivalents with better performance are available today. Because Vgs(th) is minimum 1V, the emitter-follower-buffered outputs from the driver stage are acceptable. To switch each pair in under 100ns, a total gate current of Qg/ton, or 120mA is required—the nominal 15mA of the unbuffered driver won't cut it, but the emitter followers will easily do it in 60 or 70ns.
As a simple H-bridge, this circuit has a constant-voltage supply, and... wait, but there's an inductor and stuff in there! Yes, contrary to common advice, sometimes the worst thing you can do is bypass the supply. It all depends on situation, but blindly following suggestions is rarely the correct choice! In this case, shoot-through is guaranteed during switching: the threshold voltages overlap by some 6V at least. Twice as many gate drivers would be required if dead time control were added (plus the delay logic), which is more than I want to bother with here. By making the supply "squishy", I can tolerate shoot-through much better, and manage the side-effects more easily than the alternative.
So, the action that's going on is this: when the gate voltage is switched, from anywhere between 1 to 11V (depending on the exact thresholds), both N and P will be on and shorting out the supply. If commutation only takes 70ns (reasonable, given the drive capability and gate charge), then the supply will be shorted for about as long. If we want the current to rise by no more than a fractional ampere, then the inductance must be: L = ton(Vcc - 2Vgs(th)) / Ipk, or around 2.2μH. This is a simple dI/dt snubber. This inductor builds up a current during switching (and carries load current besides), which must be discharged when switched off. The energy could be recycled with diodes and another converter, but at low power levels like this, it's not worth it, and like the deadtime control method, the added complexity further detracts from the aim of the circuit (to demonstrate a simple class D amplifier system). So instead, the inductor is simply damped with a diode and resistor. Why a diode? Without, the resistor would draw current during commutation, rather than allowing that event to be cushioned by the "springy" inductance alone. With a diode, only the 'flyback' energy released from the inductor following the event is dissipated.
Measured drain (output) waveforms, same switching edges as the gate drive waveform (2V/div vertical, both channels; channel 2 colorized to stand out; 50ns/div horizontal). The purple trace kind of disappears amid the squashed junk, but it's a safe bet it's doing the same thing (high frequency squigglies with DC around 1V). The shoot-through region is about 30ns long (for the falling gate edge, which was slower), matching the corresponding region in the gate waveforms. Following shoot-through, the supplies rebound (ground apparently has fairly high inductance, rebounding about 1.5V; the supply has more inductance (intentionally), and that spike is caught by the diode and resistor. Strangely, the supply doubles back for a sharp spike, which may be amplified (shoot-through on rebound?), since the gate waveform has a similar spike. I'd have to take more in-depth measurements to determine the cause. The rising and falling edges themselves are quite fast (10ns or under), which shows the transistors are amplifying (and, in essence, clipping) the gate drive waveform, speeding it up. Which is something to keep in mind when concerned with EMI: each switching stage tends to speed up the signal (up to its maximum switching speed).
Output waveforms (output terminals, plus and minus, relative to input common). No input signal, no load. (This time using the TDS460 scope, rather than the 475.) Math is the sum Ch2+Ch4, twice the common mode noise. The residual ripple is 1.6V RMS (Ch2-Ch4), not terrible really, considering it's about -22dB from what the switching transistors are doing. The common mode noise could be better (FCC would be happy with this in the single millivolts), but this goes to show how important layout is. Ch2 has much more prominent spikes on it, probably due to asymmetry in the filter choke, or longer trace lengths on its filter capacitors. To get this down to approved levels, I would run the signals through another stage or two of filtering, over and between ground plane, well away from the switching nodes. The input and power leads would get similar treatment.
This is the complete schematic. A couple of things missed above: the PWM comparator (too boring: just the other comparator half, with a tinge of positive feedback to keep it solid), supply bypass and filtering (shown by the output stage), and the output filter network (shown, but not talked about, above).
The output filter deserves some discussion. In order to have as fast a response as possible, it should have as high a cutoff frequency as practical. There is an obvious trade-off between output ripple and passband range. In practice, ripple at the fundamental is tolerable, especially if it's differential mode only. In this case, with an operating frequency of 120kHz, it falls below the FCC Part 15 cutoff for conducted emissions (which is 150kHz), so it's not very important how large this ripple is, nor how long the wires are that can be connected to it (put your speaker boxes on the other side of your house, who cares!). If this had a higher operating frequency (over 200kHz is very typical), it would become important. Note, by the way, FCC is primarily concerned with common mode signals: differential ripple in cables isn't considered.
The filter shown has a resonant frequency of F = 1/(2π√(LC)) or about 53kHz (note the inductors act in series, on the same core, so the effective inductance is 40μH). The impedance is Z = √(L/C) or 13.5Ω, a bit high for a bridged amplifier (a 4 or 8 ohm load would be more typical), but hardly a problem in a circuit where impedance matching is thrown to the wind (the source is nearly zero impedance, while the load may be anywhere from a nice well-behaved resistive load, to an open circuit, to a moderately reactive load anywhere inbetween). In practice, the response will be somewhere between overdamped (with a low resistance load) to underdamped (open circuit or reactive). The 51 ohm and 0.22μF dampen things without cutting into response too badly.
The time-domain response of the filter (at the H-bridge side) is also important. Cycle to cycle, the inductor can be treated as an inductance to ground and that's it (a crude approximation, but good enough within 20% or so). The voltage waveform is square, so the current waveform will be triangular, Ipp = 2Vcc/(2FL) (double supply because H-bridge, and using the 40μH figure for L), or 2.5A. This is well within the transistors' ratings, but will contribute to idle power dissipation (in addition to switching losses due to shoot-through). To reduce inverter ripple, a larger inductance could be chosen, and to keep the cutoff frequency constant, a smaller filter capacitance as well. But such a filter would be heavily overdamped by the nominal load, dropping the cutoff frequency substantially. A smaller inductance isn't really desirable due to ripple, so the value I chose was quite reasonable.
The filter choke is followed by a common-mode choke. This is kind of optional, but helps clean up the trash that the FCC might not find so appealing. In practice, the switching times and pulse widths of the two sides of the H-bridge won't be perfectly symmetrical, and there will be common mode components at the fundamental and harmonics. Filtering this with a common-mode choke helps clean things up further, plus the leakage inductance (which is intentionally high, as wound) helps take more edges off the differential signal. The 112μH inductance shown acts between the 0.1μF caps in parallel, placing the cutoff around 33kHz: not very low (it could easily be kHz for best results), but the attenuation over 150kHz will be good. Likewise, the differential filtering will be on the order of 1μH and 0.1μF, or 500kHz, again helping to take the edge off.
Construction details: the differential filter choke was wound on a T50-52 powdered iron core, as shown. This is a fairly lossy material, and likely has a Q factor around 20. In operation, it gets rather warm, which is due in some part to the relatively fine wire used (which carries about 0.7A RMS), but mostly due to the core losses. The applied reactive power is around 9VA, so the power dissipation will easily be 0.45W for a Q of 20. (A rough estimate puts it closer to a Q of 10.)
The common-mode filter choke doesn't handle much reactive power, so there isn't much analysis required for it. It is worth noting the winding method: a true common-mode choke could be made by winding a twisted pair, and it would have very low leakage inductance—good for transmitting signals, but not so desirable when attenuating high frequencies. Instead, the two windings can be wound together, in the same direction (poloidally) through the core, but in opposite directions (toroidally) along the core. Rather than a bifilar or twisted pair winding, they act as separate solenoids linked by a core, and thus there is more leakage, roughly 1/μr times the self inductance, or (given the #43 core having μr around 700) fractional μH range. I hadn't measured the actual leakage, and the 1μH figure used above is only a crude approximation.
Idle Conditions: Supply 11.72V; input grounded, no load connected to output; ambient 24°C; PCB in near-vertical orientation; weak ambient draft.
Measurements: Supply current: 190mA (2.22W dissipated). Output transistor temperatures: 56°C, 61°C; differential filter coil: 62°C. Output ripple (Vout1 - Vout2): 1.6V RMS, common mode (Vout1 + Vout2) 60mV. Minimal over 20MHz. (I don't have a spectrum analyzer or FFT handy to do high frequency measurements; the waveforms change little in appearance between 20MHz and 350MHz bandwidth, suggesting <2mV beyond 20MHz.)
Discussion: Clearly, core losses in the differential coil are significant, and this circuit would benefit from a lower loss material, like Kool-mu (typically a Q around 30), or a gapped ferrite core (very high Q). Switching losses are also significant, and even a simple circuit like this would benefit from dead time control if efficiency is a concern.
Under Load Conditions: 12.05V supply, 1kHz sine input (adjusted for 6.06V RMS output, pictured above), 5Ω load resistor. (Ambient and orientation same as above.)
Measurements: Supply current: 0.898A (10.82W consumption); output power: 7.3W (efficiency 67%); output transistor temperatures: 81°C and 82.5°C; differential filter coil: 69°C.
Discussion: The differential coil temperature hardly rose, despite delivering another ampere: core losses are dominant, and again, a lower loss core would help. Overall efficiency is lower than desired, and saving those idle losses would more than suffice. The transistors are running much warmer, though with 70°C headroom before reaching the 150°C ratings, even more output capacity is available, or at a higher ambient temperature (or a de-rating scale between them). The distortion is unfortunately quite poor at 1kHz, and isn't much better at larger voltage swing.
Here are photos of the top and bottom sides (click to enlarge):
A rather nice PCB if I do say so myself; alignment between top and bottom layers must be within 5 thousandths of an inch, the best I've ever done. If I had had the stuff to do plated-through holes, solder mask and silk screen, it would've been as good as a commercial board.
Simulated step response: some feed-forward action due to the non-inverting error amplifier, followed by a third order recovery, more or less critically damped. The simulation is kind of bad at making a DC potential out of random AC fluctuations, so the steady state isn't so steady. This can be addressed by increasing the precision of the simulation, but that costs CPU time, taking many minutes to generate the millisecond sample shown here. Since we know that it's going to stabilize, this can be ignored safely as a simulation artifact.
Compensating this type of circuit (with a second order filter in the loop) isn't easy, and typically only a compromise is possible. This has roughly equal over- and under-shoot, and an overdamped recovery. High frequency response will be attenuated, and the overall passband won't be flat out to 20kHz (within, say, 3dB). Reproducing 20kHz through all the filters and switching is a difficult task anyway, not something this simple circuit is up to.
Measured step response (back on the '475 scope), 0.5V/div vertical, 100μs/div horizontal (above), 20μs/div (below), approx. 2kHz square wave input. Note the test amplitude is smaller than in the simulation, so ripple looks relatively large. The transient behavior is almost identical (as well as can be seen over the ripple), including a better representation of the over-undershoot characteristic of the output filter. (And as expected, it stabilizes to a smooth ripple and not noise.)